Lead and manage a team of engineers in multimedia, security, or AI accelerator design, verification, and SoC integration. Develop IP front-end designs, focusing on microarchitecture and RTL design for next-generation CPUs. Propose performance-enhancing microarchitecture features, collaborating with software, architect, and performance teams. Deliver designs meeting PPA goals with production quality. Lead verification to ensure quality designs, working with physical design and power teams to meet frequency, power, and area goals. Requires 18+ years of experience with digital logic design, RTL design concepts, verification methodologies (UVM, SystemVerilog), and IP development for SoCs. Responsibilities include leading design development or functional verification teams, performing power, performance, and area characterizations and optimizations.