Senior ASIC Design Engineer, Silicon
Job Summary
Job Description
- Bachelor's degree in Electrical or Computer Engineering
- 5+ years RTL design experience (Verilog/SystemVerilog)
- ARM-based SoC, interconnect, and ASIC methodology experience
- RTL quality checks (Lint, CDC, Synthesis, UPF)
- Microarchitecture design and implementation
- Master's degree in Electrical/Computer Engineering
- Low power estimation and timing closure experience
- Experience with scripting languages (Python or Perl)
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
- 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
- Experience in ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master’s degree in Electrical/Computer Engineering.
- Experience with methodologies for low power estimation, timing closure, synthesis.
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
- Experience with a scripting language such as Python or Perl.
About the job
In this role, you will be part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality RTL. You'll solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance, power and area in mind.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform RTL development (SystemVerilog), debug functional/performance simulations.
- Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
- Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
- Communicate and work with multi-disciplined and multi-site teams.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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