Senior ASIC Design Performance Verification Engineer, Silicon
Job Summary
Job Description
This Senior ASIC Design Performance Verification Engineer role at Google involves developing custom silicon solutions for direct-to-consumer products. Responsibilities include developing performance verification test plans, analyzing performance data, and collaborating with architecture and design teams. The role requires planning and executing performance verification of next-generation IPs, interconnects, and memory subsystems. This includes utilizing constrained-random verification environments, developing stimulus, and enhancing performance monitors and scoreboard infrastructure using SystemVerilog and UVM. Verification of low-power optimization impact on performance is also crucial. The ideal candidate possesses strong experience in RTL simulation, performance verification for IPs, and familiarity with various interconnect protocols and memory technologies.
Must have:
- 5+ years experience in RTL simulation using SystemVerilog and UVM
- 5+ years experience in performance verification for IPs
- Develop performance verification test plans
- Analyze performance data and conduct reviews
- Use constrained-random verification
Good to have:
- Experience with Caches, Coherency, Memory Consistency Models
- DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers
- Interconnect Protocols (AHB, AXI, ACE, CHI, CCIX, CXL)
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
- 5 years of experience in simulating digital reasoning at Register-Transfer Level (RTL) using SystemVerilog and UVM.
- 5 years of experience in performance verification for IPs.
Preferred qualifications:
- Experience in Caches Hierarchies, Coherency, Memory Consistency Models, Double Data Rate SDRAM/Low Power Double Data Rate SDRAM (DDR/LPDDR), Peripheral Component Interconnect Express (PCIe), Packet Processors, Security, or Clock and Power Controllers.
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Develop a performance verification test plan from architecture specifications and goals; analyze performance data and conduct reviews with architecture and design teams to get a sign-off.
- Plan and execute the performance verification of the next generation configurable infrastructure Internet Protocols (IPs), interconnects and memory subsystems.
- Use constrained-random verification environments and develop stimulus, enhance existing performance monitors and scoreboard infrastructure using SystemVerilog and Universal Verification Methodology (UVM).
- Verify the impact of low power optimization on performance.
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