Senior DFT Engineer

8 Hours ago • 3 Years +

Job Summary

Job Description

As a Senior DFT Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, with a focus on DFT and ATPG. You will work with cross-functional teams to develop solutions and meet performance requirements. The role involves in-depth knowledge of DFT concepts, hands-on experience in DFT insertion, ATPG pattern generation/verification, MBIST verification, post-silicon bring-up/yield analysis, expertise in test mode timing constraints definition, scripting languages, and simulation of test vectors. The ideal candidate should be able to work in a dynamic international team, learn and adapt to new tools and methodologies, and have excellent problem-solving skills.

Must have:

3+ years in DFT, ATPG, Scan Insertion, MBIST, JTAG
In-depth knowledge of DFT concepts
Hands-on experience in DFT insertion, ATPG generation/verification
Expertise in test mode timing constraints definition
Expertise in scripting languages such as perl, shell

Good to have:

Experience in simulating test vectors
Knowledge of equivalence check and RTL lint tool
Ability to work in an international team

4 skills required

4 skills required for this role

Add these skills to join the top 1% applicants for this job

shell

perl

fpga

cross-functional

Job Details

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG
-In depth knowledge of DFT concepts.
-In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis
-Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
-Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc.
-Expertise in scripting languages such as perl, shell, etc.
-Experience in simulating test vectors.
-Knowledge of equivalence check and RTL lint tool (like spyglass).
-Ability to work in an international team, dynamic environment
-Ability to learn and adapt to new tools and methodologies.
-Ability to do multi-tasking & work on several high priority designs in parallel.
-Excellent problem-solving skills

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