Senior Engineer II - VLSI

43 Minutes ago • 5-7 Years

Job Summary

Job Description

The Senior Engineer II - VLSI will be responsible for the front-end implementation of IPs, including Synthesis, Logic Equivalence Checking (LEC), and Clock-Level Power (CLP). The role involves collaborating with designers and Place and Route (PNR) teams to achieve design closure, focusing on quality and debugging technical issues. The engineer will generate functional Engineering Change Orders (ECOs) using Cadence Conformal LEC and provide support to the Gate Level Simulation (GLS) team, with a strong understanding of RTL and synthesis-related warnings. This role requires a proactive individual with a strong understanding of timing constraints, low-power aspects, and Design for Testability (DFT) concepts. The engineer should be experienced in synthesis, LEC, CLP, and timing closure, with a proven ability to handle complex designs involving multiple high-frequency clocks and complex clocking schemes, alongside scripting and automation skills.

Must have:

5-7 years of experience in physical-aware synthesis.
Complete understanding of timing constraints and DFT concepts.
Experienced in synthesis, LEC, CLP and timing closure.
Experience handling complex designs, multiple high-frequency clocks.

Perks:

Competitive Compensation Package
Restricted Stock Units (RSUs)
Provisions for advanced education
Medical Insurance and Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility

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Job Details

The Opportunity

We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

What You'll do:

Responsible for front end implementation of IPs which includes Synthesis, LEC, CLP.
Collaborate with designers and PNR teams to achieve design closure with focus on Quality
Ability to debug and resolve technical issues.
Hands on functional ECO generation using Candence conformal LEC
Should be able to provide good support to Gate level simulations (GLS) team
Overall, should have good knowledge on RTL so as to understand all synthesis related warnings.

What You'll Need:

5-7 years’ experience in physical aware synthesis.
Self-motivated
complete understanding of timing constraints, low power aspects and concepts of DFT
Experienced in synthesis, LEC, CLP and timing closure
Should have handled blocks with complex designs, multiple high frequency clocks and complex clocking.
scripting and automation experience is a must.

'' We have a flexible work environment to support and help employees thrive in personal and professional capacities"

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

Competitive Compensation Package
Restricted Stock Units (RSUs)
Provisions to pursue advanced education from Premium Institute, eLearning content providers
Medical Insurance and a cohort of Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.