Senior Hardware Engineer, Integrated Circuit Design, Quantum AI

1 Month ago • 3-5 Years • Research & Development • $147,000 PA - $216,000 PA

Job Summary

Job Description

As a Senior Hardware Engineer in Integrated Circuit Design for Quantum AI, you'll support the physical design and simulations of quantum processors and related devices. Responsibilities include device layout, finite element simulations, integrating design metadata, expanding design infrastructure, and automation. You will work closely with cross-functional teams to produce complex processor designs, integrate prototypes, and collaborate with foundries on custom PDKs and design rule checks. The goal is to contribute to the development of a large-scale quantum computer capable of solving complex problems.
Must have:
  • Bachelor's degree in relevant field
  • 3+ years experience in physics research
  • Proficient in Python or similar
  • Experience with CAD layout and verification tools
  • Electromagnetic and Finite Element Simulation expertise
Good to have:
  • Master's or PhD
  • Knowledge of K-Layout or equivalent
  • Familiarity with IC fabrication
  • Superconducting circuit and quantum computing knowledge
Perks:
  • Bonus
  • Equity
  • Benefits

Job Details


Minimum qualifications:

  • Bachelor's degree in Physics, Computer Science, Electrical Engineering, or equivalent practical experience.
  • 3 years of experience working in a physics research environment utilizing software engineering tools for layout design and development.
  • Experience with Python or other programming languages.
  • Experience with programmatic CAD layout and verification tools.
  • Experience with Electromagnetic simulations and Finite Element Simulation tools (e.g. Sonnet, HFSS, Comsol).

Preferred qualifications:

  • Master's degree or PhD in Physics, Computer Science, Electrical Engineering, or equivalent practical experience.
  • 5 years of experience working in physics research environment utilizing software engineering tools for layout design and development.
  • Knowledge of Layout vs Layout, Layout vs Schematic, K-Layout or equivalent CAD viewer.
  • Familiarity with IC fabrication techniques and processes.
  • Familiarity with Superconducting circuit architectures and quantum computing.

About the job

As an Integrated Circuit Designer, you will support the physical design and simulations of quantum processors and associated analog, DC, and RF devices and help to build infrastructure for design production. You will work closely with other members of our team to produce complex processor designs and integrate prototype designs through predefined layout and simulations workflows. Your activities will span from laying out mask schematics and running finite element simulations to integrating design metadata in various software tools and expanding on current design infrastructure and automation.

The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.

The US base salary range for this full-time position is $147,000-$216,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

  • Support complex Quantum processor design projects including device layout and simulations.
  • Work on programmatic layout and simulation infrastructures to speed up and simplify layout workflow from initial layout to final tapeout.
  • Work closely with other teams to maintain and improve layout integration tools into device probing, packaging and measurement.
  • Work with foundries to support custom process design kits (PDKs) and design rule check.

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