Senior Principal Design Engineer
Job Description
- Experience leading System testing efforts for SERDES
- Experience in PCIe/UCIe LTSSM states is a plus
- 1-2 years of experience in FPGA Design and Schematic design
- IP/SoC Physical Layer Electrical Validation experience
- Familiarity with Verilog RTL coding for FPGA
- 10-15 years experience in Post-Silicon PHY testing
- 2-3 years of management experience leading engineers
- Experience in Physical Layer and Protocol Layer SERDES
- Debug skills using lab equipment like Oscilloscopes
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
JOB Responsilibilities:
BE/BTECH/ME/MTECH
The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.
What we do :
• Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators.
• Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team)
• Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet.
• Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release.
• Engage in interop and Customer Debug.
What you'll gain :
• Chance to work on cutting edge SERDES IP's from Cadence. Refer to Cadence Website for more details on our SERDES IP's.
• Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration.
• Hardware and Subsystem design expertise.
• Experience in deploying and debugging your Solutions in different customer environments.
What we are looking for :
Minimum Qualifications:
• 10-15 years (with Btech) or 10 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 2-3 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
Preferred Qualifications:
• Experience leading System testing efforts for SERDES solutions.
• Experience in PCIe/UCIe LTSSM states is a plus.
• 1-2 years of experience in FPGA Design and Schematic design.
• 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
• Familiarity with Verilog RTL coding for FPGA, python,C/C++
• Good communication skills
Seasoned Systems Validation engineer who can lead SERDES projects (PCIe/CXL/UCIe) and mentor Juniors
