Senior Signal and Power Integrity Engineer - Hardware

We are now looking for a Senior Signal & Power Integrity Engineer!

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle!

What you'll be doing:

• Work on crafting creative Signal Integrity solutions to complex system design problems.

• Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D EM tools.

• System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, LP5X and other interfaces.

• Constant improvements of SI models using data from lab measurements and/or modelling tool/methodology updates.

• Substrate and board layout SI guidelines creation, review and post layout SI extractions.

• Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools.

• Opportunity to work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.

What we need to see:

• BS/MS-Electrical Engineering or equivalent experience

• 6+ years of industry experience.

• Strong technical background in applied electromagnatics, transmission line theory and signal processing will be highly valued.

• SI work on one or more signaling standards like PCI express, USB, SATA, HDMI, HBM, DDR5, GDDR6, LPDDR5X, etc.

• Hands on use of 3-D modeling tools like ANSYS HFSS/Q3D, 2.5-D with ANSYS SIWAVE or similar and 2D such as Ansys2D.

• Familiarity with a system level timing or loss budget including silicon, package and board impairments.

• Familiarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro will be a plus.

Ways to stand out from the crowd:

• Expertise in one or more of the high speed interface SI/PI design on any industry standard system platforms.

• Experience with lab measurements, debugging, SI lab correlation using oscilloscope/ spectrum analyzer/ VNA.

• Knowledge of circuit design, board/pkg technology & design, link architecture, timing budget methodologies.

• Familiarity with PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations.