Senior Silicon DFT Lead, Google Cloud

8 Months ago • 8-12 Years

Research Development

Job Description

As a Senior Silicon DFT Lead at Google Cloud, you'll be a key player in designing, implementing, and verifying DFT solutions for large-scale ASICs. This involves developing DFT strategies and architectures, collaborating with other engineering teams (Design, Verification, Physical Design), managing the DFT team's workload, and ensuring that DFT requirements are met throughout the ASIC development flow. You'll lead DFT execution for silicon projects, from planning and execution to quality control and sign-off. The role requires expertise in ATPG methods, DFT techniques and tools, and leadership experience. You'll contribute to the innovation behind Google's direct-to-consumer products, shaping the next generation of hardware experiences.

Good To Have:

Master's degree in EE
JTAG/iJTAG experience
Post-silicon test experience
SoC cycles, silicon bring-up, debug
Fault modeling techniques

Must Have:

8+ years ATPG experience
4+ years people management
ASIC DFT design & verification
DFT architecture & insertion
Lead DFT activities throughout ASIC flow

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
4 years of people management experience developing employees.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the DFT Senior Engineer, you will play a crucial role in DFT Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project lifecycle, and providing sign-off DFT to tapeout.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.