Senior Staff Engineer, Memory Fault Management Architect

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Conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era of Data center, it is easier to track the field failure information. With this data set, Fault management team’s role is finding DRAM failure mode, abnormality and failure rate projection.

You will be part of an incubation team working on in-field telemetry intended to transform the Customer Quality Experience for Samsung memory products. Fault Management is the future of quality to minimize system downtime within AI/ML hardware deployments and workloads of the future. We analyze trends and patterns from enormous memory fleet telemetry to bucketize failures and perform virtual root-cause analysis. Telemetry analysis helps us design solutions to proactively avoid system downtime. We conduct research and develop both in-house and collaboratively in the industry with the opportunity to publish our findings through whitepapers and conferences. We are looking for innovative and passionate thinkers who can work in a start-up environment and are excited to shape the future of data centers around the world. Join us in our mission!

What You'll Do

• Based on the knowledge of  SOC controller and memory operation including RAS feature, find and recommends better solution to mitigate the field DRAM failure rate.
• Needs to communicate better ECC scheme to customers based on Samsung DRAM failure mode(DQ and burst)
• Interface with customers to establish the value add of enabling in-field fault management architecture
• Contribute to the standardization of DRAM/HBM failure logging in the OCP.
• Propose and develop platform RAS (Reliability Availability Serviceability) algorithms for memory fault management such as page offlining, hPPR and conduct POC with known failure DIMMs in the real server and application.

Location: Hybrid with at least 3 days in office in San Jose, CA office location remainder of time to work remotely

Job ID: 42448

 What You Bring

• Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years hardware fault management, reliability, data center fleet management experience or related technical field preferred
• Knowledge of platform memory subsystem, platform RAS (Reliability Availability Serviceability) such as ECC, page offlining, hPPR and hardware sparing.
• ECC design and verification and reverse engineering experience.
• Understanding on the address mapping between CPU and memory.
• Memory controller register modification.
• Linux kernel commit experience.
• DRAM and HBM failure mode understanding.
• Excellent communication and interpersonal skills.
• Ability to work independently and as part of a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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