As a Senior System Debug Engineer, you will define, develop, and perform functional validation for CPUs, focusing on validation of the CPU internals and CPU integration in system-level features for Intel performance and power efficient cores. You will apply various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. You will review proposed design changes to assess impact on validation plans, tasks, and timelines. You will develop CPU validation methodologies and test plans, execute validation plans, and collaborate with other engineers for design optimization, troubleshooting, and failure analysis. You will apply knowledge of CPU core architecture, processor microarchitecture, and design. You will perform silicon debug to identify root causes and resolve all functional and triage failures for CPU issues. You will test interactions between various CPU features using validation infrastructure. You will develop post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. You will publish CPU validation reports summarizing all validation activities performed, review results, and communicate to relevant teams. You will work with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for CPU interfaces and to meet desired product specifications. You will develop content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). You will engage in all phases of the product life cycle, develop and validate content and infrastructure, and bug hunts in multiple environments (simulation, emulation, FPGAs) to ensure silicon readiness.