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Silicon AI/ML DFT Engineer, TPU, Google Cloud

Silicon AI/ML DFT Engineer, TPU, Google Cloud

1 Month ago • 3 Years + • Research & Development • Quality Assurance

About the job

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Job Description

This role involves designing and implementing advanced Design for Testing (DFT) methodologies for AI/ML hardware acceleration, specifically Google's Tensor Processing Units (TPUs). Responsibilities include defining silicon test strategies, implementing DFT specifications for next-generation SoCs, inserting and verifying DFT logic, and collaborating with test engineers on post-silicon debug. The engineer will contribute to reducing test costs, increasing production quality, and enhancing yield. The position requires expertise in DFT architecture, EDA tools, and ASIC flows, with a focus on TPU architecture and its integration within AI/ML systems.

Must have:

Bachelor's degree in Electrical Engineering or related field
3+ years experience in DFT specification, architecture, and insertion
Experience with EDA test tools (Spyglass, Tessent)
ASIC DFT synthesis, STA, simulation, and verification
Develop DFT strategy and architecture
Insert DFT logic and MBIST logic
Document DFT architecture and test sequences

Good to have:

Master's degree in Electrical Engineering
IP integration experience (memories, test controllers, TAP, MBIST)
SoC cycle experience (silicon bring-up, debug)
Fault modeling experience
Experience working with ATE engineers

Minimum qualifications:

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
3 years of experience in DFT specification definition architecture and insertion.
Experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent).
Experience with ASIC DFT synthesis, STA, simulation, and verification flow.

Preferred qualifications:

Master's degree in Electrical Engineering.
Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
Experience in SoC cycles, including silicon bring-up and silicon debug activities.
Experience in fault modeling.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, Implement, and create DFT specifications for next generation SoCs while working with the DFT Organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO.
Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve test quality and support post-silicon test team.

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Google

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