Silicon DDR Bringup and Validation Engineer

3 Months ago • 5 Years +
Quality Assurance

Job Description

The Silicon DDR Bring-up and Validation Engineer will be responsible for initiating and validating DDR subsystems within Rivos SOC designs. This role requires a strong understanding of advanced DDR design for server applications, encompassing physical design, logic, performance, system, and software aspects. Key responsibilities include generating tests, configuring test infrastructure, planning and executing bring-up procedures, and developing and implementing validation plans for DDR systems. The position is intended for technical lead or senior technical staff roles, involving leading an engineering team to design and execute DDR subsystem silicon bring-up plans, perform functional and performance tests, and ensure the subsystem meets product requirements. Collaboration with cross-functional teams, vendor engagement, issue debugging, root-cause analysis, sensitivity experiments for optimization, and continuous improvement of processes are also core duties.
Good To Have:
  • Work with vendors and partners
  • Drive continuous improvement of processes
  • Maintain up-to-date knowledge of technology trends
  • Experience with waveform viewers and emulation
  • Ability to develop environment and tools
  • Highly self-motivated
  • Productive under aggressive schedules
Must Have:
  • Lead DDR subsystem silicon bring-up and validation
  • Collaborate with cross-functional teams
  • Debug and root-cause issues
  • Design and execute sensitivity experiments
  • In-depth knowledge of DDR subsystems for servers
  • Experienced in C/C++ and Python
  • Knowledge of verification methodologies, Verilog simulation
  • Experience in silicon debug
  • Experience with lab instruments
  • Strong problem-solving and communication skills

Add these skills to join the top 1% applicants for this job

cross-functional
cpp
python

The role of the Silicon DDR Bring-up and Validation Engineer involves the initiation and validation of the DDR subsystems within Rivos SOC design. This position demands a comprehensive grasp of cutting-edge DDR design tailored for server applications, covering aspects such as physical design, logic, performance, system, and software. Responsibilities include test generation, configuring test infrastructure, planning and executing bring-up processes, and developing and executing validation plans specifically for DDR systems. Currently, the intention is to fill technical lead or senior technical staff positions for this role.

Responsibilities

    • As a lead, you will lead an engineering team responsible for designing, implementing and executing DDR subsystem silicon bring-up plans, including functional and performance tests, to validate the subsystem for the silicon product to meet the product requirements.
    • Collaborate with cross-functional teams including design, architecture, firmware, and software to ensure successful subsystem bring-up and validation.
    • Work with vendors and partners to ensure successful subsystem bring-up and validation, including reviewing and providing feedback on vendor documentation, and coordinating with vendor support teams.
    • Debug and root-cause issues found during subsystem bring-up and validation, and work with cross-functional teams to implement corrective actions.
    • Design and execute sensitivity experiments to fine-tune and optimize DDR subsystems for enhanced performance and power efficiency.
    • Drive continuous improvement of subsystem bring-up and validation processes and methodologies, including automation, tool development, and documentation.
    • Maintain up-to-date knowledge of the subsystem technology and industry trends.

Requirements

    • In-depth knowledge of system architecture, performance/power, and software of DDR subsystems for server applications.
    • Experienced level knowledge of C/C++ and Python.
    • Relevant knowledge of verification methodologies, Verilog simulation, waveform viewers, and emulation.
    • Experience in silicon debug for logic, software, and physical issues.
    • Experience with lab instruments such as logic analyzers and oscilloscopes.
    • Strong ability to triage issues and develop environment and tools.
    • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
    • Ability to work well in a team and be productive under aggressive schedules.

Education & Experience

    • PhD, Master’s Degree or Bachelor’s Degree with more than 5 years of experience in DDR technical subject area.

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