Silicon Design Verification Engineer
Job Summary
Job Description
- Bachelor's degree in relevant field
- 3+ years of experience with UVM and SystemVerilog
- Experience in developing verification testbenches
- SystemVerilog Assertions (SVA) experience
- Collaboration with design and architecture teams
- Master's or PhD in Electrical Engineering/Computer Science
- Experience in low-power design verification
- Bonus
- Equity
- Benefits
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience in developing and maintaining verification testbenches, test cases, and test environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience in low-power design verification.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape out.
- Collaborate with architecture, design teams, Sival teams in defining the overall verification of the SoCs.
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