Job Description
Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification. Responsibilities include defining DFT strategy and methodologies, designing DFT features, defining test structures, debug structures, and test plans, creating test vectors or overseeing their creation, collaborating with the physical design team to close requirements, validating DFT requirements, working with designers to increase test coverage, debug observability and flexibility, verifying post-PD designs meet DFT requirements, and working with verification engineers, stepping in to do run tests when needed.
Good To Have:
- Python scripting
- Shell scripting
- Makefiles
- TCL
Must Have:
- Define DFT strategy and methodologies
- Design DFT features
- Define test structures and plans
- Create test vectors
- Collaborate with physical design
- Validate DFT requirements
- Increase test coverage
- Verify post-PD designs
- Digital logic design knowledge
- DFT concepts knowledge
- Verilog and simulators
- Verilog / SystemVerilog knowledge
- Problem-solving skills
- Teamwork and communication
Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.
Responsibilities
- Define DFT strategy and methodologies
- Design the DFT features
- Define test structures, debug structures, and test plans
- Create test vectors or oversee their creation
- Collaborate with physical design team to close requirements
- Validate DFT requirements are being met
- Work with designers to increase test coverage, debug observability and flexibility
- Verify post-PD designs meet DFT requirements
- Work with verification engineers, stepping in to do run tests when needed
Requirements
- Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
- Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
- Knowledge of Verilog and experience with simulators and waveform debugging tools
- Knowledge of Verilog / SystemVerilog
- Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
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