Silicon Digital Design Verification Engineer
Job Description
- Experience creating detailed block-level DV strategies and plans
- Experience with UVM, VMM, OVM methodologies
- RTL, low power, gate level (GLS) and formal verification experience
- Mixed signal design and verification experience
- Knowledge of analog design basics and SystemVerilog analog modeling
- Proficiency in scripting languages (Python, etc.)
- 5+ years experience in digital verification using SystemVerilog for ASIC designs
- Experience developing and maintaining DV testbenches, test cases, and environments
- Understanding of design specifications and collaboration with design engineers
- Identifying key coverage metrics and progress towards tape-out
- Bonus
- Equity
- Benefits
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience leading digital verification using SystemVerilog for ASIC designs.
- Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.
Preferred qualifications:
- Experience in creating detailed block-level design verification strategies and plans.
- Experience creating or using verification components and environments in methodology (UVM, VMM, OVM).
- Experience in RTL, low power (e.g., Unified Power Format or Common Power Format), gate level (GLS) and formal verification techniques.
- Experience working with mixed signal (e.g., Analog Mixed Signal and Digital Mixed Signal) designs and mixed mode verification.
- Knowledge of analog design basics and experience writing SystemVerilog models of analog blocks using advanced techniques (real-number modeling (RNM), Verilog-AMS, etc.).
- Proficiency in one or more scripting languages (Python, etc.)
About the job
Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Responsibilities
- Plan and execute on the verification of digital and mixed signal design blocks by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Identify and implement key coverage metrics for stimulus and corner-cases to identify verification holes and to show progress towards tape-out.
- Design verification and work with stakeholders to come up with detailed execution plans, schedule, dependencies and deliverables.
- Work closely with system, software, design, Design for testing (DFT) and physical implementation stakeholders to make technical decisions.
- Be the primary point of contact for functional verification for cross-functional teams and lead or drive the building of reusable design verification (DV) infrastructure components.
