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Silicon Hardware Architecture Modeling Engineer, TPU, Google Cloud

Karnataka, India (On-site)

Silicon Hardware Architecture Modeling Engineer, TPU, Google Cloud

1 Month ago • 3 Years + • Research & Development

About the job

3 skills required for this role

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cpp

python

innovation

Job Description

As a Silicon Hardware Architecture Modeling Engineer at Google Cloud, you'll be at the forefront of AI/ML hardware acceleration, developing cutting-edge TPU (Tensor Processing Unit) technology. You'll work alongside a talented team to push the boundaries of custom silicon solutions, powering Google's most demanding AI/ML applications. Your expertise in design and verification will be crucial for verifying complex digital designs, with a focus on TPU architecture and its integration within AI/ML-driven systems. You'll be responsible for characterizing and benchmarking ML workloads, conducting performance and power analysis, developing architectural and microarchitectural models, and collaborating with hardware and software teams for efficient co-design. You'll also be involved in proposing capabilities and optimizations for next-generation TPUs and the overall chip roadmap.

Must have:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
3 years of experience in computer architecture performance analysis and optimization or a PhD degree
Experience developing software systems in C++
Experience in applying computer architecture principles to solve open-ended problems
Experience in analyzing workload performance and creating benchmarks

Good to have:

Experience in hardware and software co-design
Experience developing in Python
Knowledge of processor design or accelerator designs and mapping Machine Learning (ML) models to hardware architectures
Knowledge of design of digital logic at the Register Transfer Level (RTL) using Verilog

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
3 years of experience in computer architecture performance analysis and optimization, or a PhD degree in lieu of industry experience.
Experience in developing software systems in C++.

Preferred qualifications:

Experience in applying computer architecture principles to solve open-ended problems.
Experience in analyzing workload performance and creating benchmarks.
Experience in hardware and software co-design.
Experience developing in Python.
Knowledge of processor design or accelerator designs and mapping Machine Learning (ML) models to hardware architectures.
Knowledge of design of digital logic at the Register Transfer Level (RTL) using Verilog.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

You will work with hardware and software architects to model, analyze, and define next-generation Tensor Processing Units (TPU).

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Work on Machine Learning (ML) workload characterization and benchmarking.
Conduct performance and power analysis and quantitatively evaluate proposals.
Develop architectural and microarchitectural models to enable quantitative analysis.
Collaborate with partners in hardware design, software, compiler, ML model and research teams for effective hardware/software codesign.
Propose capabilities and optimizations for next-generation Tensor Processing Units (TPU) and chip roadmap.

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About The Company

Google

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