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Silicon RTL Design Lead, Google Cloud

Silicon RTL Design Lead, Google Cloud

1 Month ago • 15 Years + • Research & Development

About the job

5 skills required for this role

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cpp

level-design

python

perl

innovation

Job Description

This role involves leading a team of engineers in the design and development of complex IPs or subsystems for Google Cloud's TPU (Tensor Processing Unit) technology. Responsibilities include defining micro-architecture specifications, performing RTL development, SoC integration, and participating in verification, synthesis, and silicon bring-up. The ideal candidate will have extensive experience in ASIC/SoC development with Verilog/SystemVerilog and a strong understanding of micro-architecture, design verification, and high-performance/low-power design techniques. The position requires collaboration with multi-disciplinary teams across multiple sites to deliver high-quality designs for next-generation data center solutions. This role is crucial to advancing Google's AI/ML hardware acceleration capabilities.

Must have:

15+ years ASIC/SoC development (Verilog/SystemVerilog)
Experience in micro-architecture and IP design
ASIC/SoC design verification, synthesis, timing/power analysis, DFT
Lead engineering teams
RTL development, subsystem & SoC integration

Good to have:

Python, C/C++, or Perl programming
SoC design & integration flows
Processor design, accelerators, bus architectures, NoC, memory hierarchies
High-performance and low-power design techniques

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
15 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
Experience in micro-architecture and design of IPs and Subsystems.
Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

Experience with programming languages (e.g., Python, C/C++ or Perl).
Experience in SoC designs and integration flows.
Knowledge of processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.
Knowledge of high performance and low power design techniques.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center solutions.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Lead a team of Engineers in the Bangalore design organization to deliver complex IPs or Subsystems. Communicate and work with multi-disciplined and multi-site teams.
Define uArch specifications and block level design documents containing interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development, subsystem and SoC Integration and Lint/CDC/FV/UPF checks.
Participate in simulation debugs, synthesis, timing/power closure, and silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.

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