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SOC Design Verification Lead/Manager

Karnataka, India (On-site)

SOC Design Verification Lead/Manager

2 Months ago • 10 Years + • Research & Development

About the job

5 skills required for this role

Test your skills to join the top 1% applicants for this job

prototyping

python

perl

scalability

networking

Job Description

Lead SOC Design Verification for high-performance chiplets and microcontrollers. 10+ years experience in System Verilog, UVM, UPF, scripting languages (Python, Tcl/Tk, Perl), and EDA tools like Synopsys/Cadence/Tessent. Strong leadership skills to manage a team.

Must have:

System Verilog
UVM Expertise
EDA Tools
Leadership Skills

Good to have:

RISC-V Design
Formal Verification
Low Power Design
ISO2626/FuSa

Perks:

Growth Path
Competitive Benefits

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Seeking experienced SOC DV (Design verification) Lead/Manager to lead the Micro-architecture, Integration and RTL development of High-Performance Data Processing Unit Chiplets and Automotive Microcontrollers. The Candidate will be responsible for all aspects of the Design Verification including schedule, test code, test bench development, and documentation. The candidate will be additionally responsible for all emulation/prototyping and low-level driver software development.

Minimum Qualifications:

Bachelors or Masters equivalent in Computer Science, Computer Engineering, Electrical Engineering or related fields.
10+ years of experience in Design Verification of high performance SoCs.
Knowledge of System Verilog, C language, UVM, UPF and Verification IP environments.
Expertise in scripting languages like Python, Tcl/Tk, Perl etc.
Experience with major EDA tool vendor tools like Synopsys/Cadence/Tessent is desirable. Hands on knowledge of Synopsys Tools is preferable.
Hands on knowledge of bus architecture like AXI/AHB/equivalent protocols, CPU cores and peripherals.
Excellent analytical and problem-solving skills, with great execution focus.
Good leadership capabilities to lead a team of engineers and contractors to accomplish the organization goals.

Preferred Qualifications:

Experience with designing RISC-V, ARM and/or MIPS CPU
Understanding of low power microarchitecture techniques
Experience with ISO2626/FuSa
Experience in Formal verification, UVM and other such methodologies.

Here’s what you can expect from us:

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

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