SOC Power Estimation Engineer
Job Summary
Job Description
- 3+ years experience with low power RTL and physical design
- Experience with scripting languages (Python, Perl)
- Power estimation and analysis at RTL and Netlist levels
- Collaboration with architecture and design teams
- Experience in SoC architecture, power management, and clocking architecture
- Experience with RTL level power estimation/analysis tools
5 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with low power RTL and physical design techniques.
- Experience with scripting languages (e.g., Python, Perl).
Preferred qualifications:
- Experience in System on a Chip (SoC) architecture, power management architecture, clocking architecture.
- Experience with RTL level power estimation/analysis tools.
- Ability to work separately and as part of a team.
- Excellent problem-solving and investigative skills.
- Excellent communication and teamwork skills.
About the job
In this role, you will work with the Power team which will give an opportunity to stay up-to-date on the latest power estimation techniques, tools and even innovate new ways to make sure pre silicon power estimation correlates with post silicon. You will get a chance to work with Architects, Designers, and the Validation team to understand the system requirements and incorporate those requirements into power estimation methodologies.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Drive pre-silicon power estimation and analysis using power estimation tools both at Register-Transfer Level (RTL) and Netlist level.
- Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation.
- Drive power estimation and what-if analysis for IPs and subsystems and drive closure of projections vs goal gaps.
- Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction.
- Collaborate with the Arch Design team to define the right definition of scenarios and operating conditions to estimate the use-case power for the IP which reflects the real world usage of the IP.
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