Spring Co-Op, Mixed-Signal Modeling and Verification Engineer (UL- 64000148)

We are seeking creative and hardworking engineers interns to join our outstanding Analog/Mixed-Signal Verification, Modeling and Methodology Team. You will collaborate with systems and design teams to facilitate tops down design methodology through the development and validation of System Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. Additionally, we are seeking innovative individuals who are interested in this position which will play a vital role streamlining development methodology for our organization. We are proud of our exceptional environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!

This opportunity is available for the spring semester only. It is available only to students currently enrolled in a MS or PhD program in Electrical Engineering maintaining a GPA of 3.6 or above, and who will be returning to school for at least one semester following completion of his/her internship. Candidate must be available for full-time employment during the internship.