Sr. ESD Engineer

5 Months ago • 6 Years +

Job Summary

Job Description

The ESD Engineer is responsible for the design, simulation, characterization, and validation of I/O pad libraries, defining ESD methodology, and specifying chip and IP level ESD requirements. This role involves designing ESD protection devices and circuits, developing test structures, and driving the development of design rules. The engineer needs a holistic view of ESD/EOS protection for mixed-signal CMOS circuits. The responsibilities include designing, simulating, and optimizing I/O circuits and ESD structures, characterizing and modeling I/O libraries, releasing and maintaining I/O libraries and models, and driving ESD sign-off methodology.

Must have:

MSEE and 6+ years of experience
Holistic view of ESD/EOS protection for mixed-signal CMOS circuits
Strong fundamentals in ESD circuit design, layout, and testing
Relevant experience in IO design, including CMOS circuit design, ESD requirements
Chip-level ESD signoff experience
Must understand layout and be able to guide layout engineers
Proficiency with Cadence schematic capture, layout, and simulation tools
Ability to work independently and lead or be part of a technical team
Effective oral and written communication

Good to have:

Experience in IBIS model generation is a plus

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Job Details

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

The ESD Engineer is responsible for I/O library development, encompassing the design, simulation, characterization, and validation of I/O pad libraries. Also responsible for defining the ESD methodology and specifying the chip and IP level ESD requirements. Design ESD protection devices and circuits to meet design requirements. Develop test structures to characterize Si for ESD/LUP properties. Drive the development of design rules based on Si characterization data. Interface with Foundry on ESD library and ESD/LUP rule development activities. The engineer needs to have a holistic view of ESD/EOS protection for mixed-signal CMOS circuits and the ability to pull pieces together to ensure no gaps or blind spots in strategy.

Responsibilities

Design, simulate, and optimize I/O circuits and ESD structures
Characterization and modeling of I/O libraries to support mixed-signal design flow
Release and maintain I/O libraries and models
Must understand ESD and latch-up requirements
Drive ESD sign-off methodology for chip & block-level projects
Technical lead capable of pulling together engineer’s new & existing methodologies to tie ESD-Latch up-IO methodologies together & get buy-in from BU’s

Required Skills and Qualifications

MSEE and 6+ years of experience
Holistic view of ESD/EOS protection for mixed-signal CMOS circuits
Strong fundamentals in ESD circuit design, layout and testing
Relevant experience in IO design, including CMOS circuit design, ESD and latch-up requirements, physical verification, and characterization
Chip-level ESD signoff experience
Must understand layout and be able to guide layout engineers
Proficiency with Cadence schematic capture, layout, and simulation tools
Ability to work independently and lead or be part of a technical team
Effective oral and written communication

Preferred Skills and Qualifications

Experience in IBIS model generation is a plus

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Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.