Sr. Staff Design for Test Engineer

Description

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world class software and silicon development.

Overview

Synaptics is looking for a Sr. Staff Design for Test Engineer to join our dynamic and growing organization. You will be responsible for architecting methodologies and flows for WLAN DFT, ATPG, automation, and pre/post Silicon debug. This position reports to the VP, Silicon Engineering.

Responsibilities & Competencies

Job Duties

• Technically Lead DFT development
• Lead work on DFT flow and methodology to insert scan, mbist, ssn, ijtag / jtag, bscan
• ATPG test pattern generation and simulation in RTL and GLS and PG with and without timing
• Analyse DFT timing paths to define exceptions and improve architecture to ease complex DFT timing paths
• Develop DFT architecture and the implementation of MBIST, SCAN, and BSCAN for multi-million gate SoCs targeted for Voice Assistant & Multimedia applications
• Collaborate with other team members to drive DFT methodology and flow to make it more efficient
• Responsible for pre-silicon validation for all the DFT logic in block/full-chip and post-silicon bring up and yield analysis
• Synthesize / optimize the DFT logic for best PPA
• Responsible for the Static Timing Closure for all the test logic in block/full-chip