Sr. Staff/Lead Engineer – Integration, Test, and Release Team

5 Days ago • 5 Years +

About the job

Summary_{By Outscal}

Lead a team of engineers responsible for CI/CD infrastructure for RISC-V based CPUs. Strong experience in embedded software automation and test infrastructure, scripting languages (Python, TCL/TK, Jenkins), and CI/CD tools is required. Experience with debugging multicore systems and Git, Makefile, GNU toolchain is essential.

Join the RISC-V Revolution!

We are seeking highly skilled Software Engineers to join our team and help us build Software Components for our RISC-V-based CPUs/Platforms. In these roles you will be involved in various aspects of CPU / Platform Software stack, from Bare metal, RTOS, Linux boot/kernel, reference libraries, tooling, simulators, FPGA based bring -up, performance benchmarks, CI/CD, test automation etc. You may also work directly with customers at all stages, including onboarding, support, and troubleshooting.

This is an exciting opportunity to work in a dynamic environment, involving interaction with many of MIPS’s engineering teams, including systems, architecture, hardware and software as we build both hardware and software grounds up!

Our aim is to build software components that not only allow our IP solutions to be well tested but also provide our customers and partners with a robust repository of software to kick start their assimilation of MIPS IP and allowing them to obtain the highest performance from hardware and software synergy.

If you are an innovative problem solver with a deep passion for embedded software and compute technologies, and love building things from grounds up, we want to hear from you!

As our mission goes, we are committed to offering “Freedom to Innovate Compute” – Join us in this mission to accelerate your impact to the larger industry and hence your growth

You will:

Lead a team of 3-5 members responsible for CI/CD (integration, test and automation) –

Mentor and Guide team members for day-day technical tasks.

Work with cross functional stakeholders from software, systems, business teams. Create project plan, track and share progress, risks.

Be responsible for the design and implementation of CI/CD infrastructure:

Scripting to automate and improve efficiency and ease of use (ex: Python, TCL/TK, Jenkins etc.)

Develop and release mechanism to reduce the time to release SDK’s and improve the test efficiency.

Github hosting and regular snapshots.

Jenkins automation – PR tests, nightly test packages

Code review bots – coding guidelines, Klocwork/MISRA C, and other policy enforcement.

Contribute to the wider RISC-V software ecosystem, helping to ensure support for the architecture in various open-source projects
Help maintain the documentation and reference implementations that our customers rely on

Ideally, you’ll have:

5+ years of practical experience in developing and maintaining embedded software automation and test infra.

Strong scripting language experience - (ex: Python, TCL/TK, Jenkins etc.)

Basic C or C++ programming experience, basic assembly level programming

Experience debugging complex multicore systems, experience with debugging tools (OpenOCD, Segger J-Link, Lauterbach)
Experience with git, Makefile, GNU toolchain and shell scripting
Experience with device drivers, virtualization, IOMMUs, power management or SoC platform security
Experience working with hardware architecture and engineering teams
Strong communication, co-working, and listening skills

Here’s what you can expect from us:

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.