STA Engineer

8 Months ago • 2 Years +

Software Development & Engineering

Job Description

NVIDIA seeks a skilled STA Engineer to join its Networking Silicon team. Responsibilities include full-chip/chiplet STA convergence, participation in floor plan design and netlist creation, optimization of timing convergence, defining and optimizing STA signoff flows and methodologies, digital partitions and analog IPs timing integration, and collaboration with logic design and DFT engineers to define and implement constraints. The ideal candidate possesses a B.Sc./M.Sc. in Electrical/Computer Engineering, 2+ years of experience in physical design and STA, proficiency in RTL2GDS and STA flows and methodologies, familiarity with EDA tools (Synopsys, Cadence), and excellent teamwork skills. This role offers the opportunity to contribute to the design of groundbreaking large-scale chips in a dynamic and rewarding environment.

Must Have:

Full-chip/Chiplet STA convergence
Floor plan & Netlist creation
STA flow & methodology optimization
Timing integration (digital & analog IPs)
Constraint definition & implementation
2+ years STA experience
RTL2GDS & STA flow knowledge
EDA tools familiarity (Synopsys, Cadence)

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NVIDIA is looking for a best-in-class STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Be in charge of full-chip/Chiplet level STA convergence from early stages to signoff.
Take part in floor plan design and Netlist creation with aim to optimize timing convergence and work efficiency.
Define and optimize, together with CAD, STA signoff flows and methodologies.
Digital Partitions' and analog IPs' timing integration, giving feedback and driving convergence.
Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including optimizing them for runtime and efficiency.

What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
2+ years of experience in physical design and STA
Proven experience in RTL2GDS and STA flows and methodologies.
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) and timing signoff (Primetime).
Great teammate.

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

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