Staff Engineer I - STA and Synthesis

8 Hours ago • 7 Years +

Job Summary

Job Description

The Staff Engineer I - STA and Synthesis role involves leading static timing analysis and synthesis for complex ASIC designs, ensuring adherence to project schedules and performance targets. The engineer will collaborate with design teams, develop timing constraint sets, and resolve timing-related issues. This role requires expertise in RTL design, optimization for area, power, and performance, understanding Clock Domain Crossing (CDC), and proficiency in EDA tools. The engineer will analyze complex timing and synthesis issues, debug simulations, and collaborate with cross-functional teams. This role reports to the Director - VLSI.
Must have:
  • 7+ years of experience in STA and Synthesis
  • Bachelor's or Master's degree in Computer/Electrical Engineering
  • Advanced RTL Design Skills
  • Optimization for area, power, and performance
  • Understanding of Clock Domain Crossing (CDC)
  • Proficiency in EDA Tools
  • Knowledge of ASIC Design Flow
Perks:
  • Competitive Compensation Package
  • Restricted Stock Units (RSUs)
  • Provisions for advanced education
  • Medical Insurance and Wellness Benefits
  • Educational Assistance
  • Advance Loan Assistance
  • Office lunch & Snacks Facility

Job Details

The Opportunity


We're looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semi's expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic STA and Synthesis Engineer to join our fun and dynamic team of talented innovators.

What You'll do:

  • Lead the execution of static timing analysis and synthesis tasks for complex ASIC designs, ensuring adherence to project schedules and performance targets.
  • Collaborate with design teams to understand timing requirements, address timing constraints, and optimize design performance across digital and analog boundaries.
  • Proficient with the use of FM/LEC to resolve equivalence issues, and also implement ECOs.
  • Develop and maintain comprehensive timing constraint sets, leveraging expertise in industry-standard scripting languages such as Python or Perl to automate constraint generation and validation processes.
  • Interface with cross-functional teams including physical design, verification, and system integration to resolve timing-related issues and drive design closure.
  • Apply deep understanding of flow methodologies and best practices to streamline design implementation processes and improve overall design efficiency.
  • Demonstrate to effectively articulate timing analysis results, provide timely updates on project status, and collaborate with stakeholders to resolve technical challenges.
  • Stay abreast of emerging technologies and industry trends, continuously enhancing skills to remain at the forefront of ASIC design methodologies and practices.
  • You will Report to Director -VLSI.

What You'll need:

  • 7+ years of experience in STA and Synthesis.
  • Bachelor's Degree or a Master's degree in Computer or Electrical Engineering.
  • Advanced RTL Design Skills.
  • Proficiency in Register Transfer Level (RTL) design.
  • Optimization for area, power, and performance.
  • Understanding of Clock Domain Crossing (CDC).
  • Techniques for reliable data transfer between clock domains.
  • Synchronizer design and analysis.
  • Understanding of RTL LINT Errors/Warnings.
  • Expertise in Low Power Design Techniques.
  • Power optimization methodologies such as clock gating, power gating.
  • Analysis and optimization for low power operation.
  • Proficiency in EDA Tools.
  • Experience with synthesis, static timing analysis, and physical design tools.
  • Knowledge of Synopsys Design Compiler, Cadence Encounter, Fusion Compiler
  • Knowledge of ASIC Design Flow.
  • Understanding of the end-to-end ASIC design flow.
  • Familiarity with Design for Testability (DFT) techniques.
  • Problem-Solving and Debugging Skills.
  • Analyze complex timing and synthesis issues.
  • Debug RTL and gate-level simulations.
  • Team Collaboration and Leadership.
  • Collaboration in cross-functional teams.
  • Leadership skills for project management and mentorship.
  • Continuous Learning and Adaptability.
  • Stay updated with advancements in ASIC design methodologies.
  • Adaptability to evolving project requirements and industry trends.

We have a flexible work environment to support and help employees thrive in personal and professional capacities.

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

  • Competitive Compensation Package.
  • Restricted Stock Units (RSUs).
  • Provisions to pursue advanced education from Premium Institute, eLearning content providers.
  • Medical Insurance and a cohort of Wellness Benefits.
  • Educational Assistance.
  • Advance Loan Assistance.
  • Office lunch & Snacks Facility.

Equal Employment Opportunity Statement

Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

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About The Company

We work to create silicon that enables the highest performing, most reliability and lowest power digital communication networks.

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