Marvell seeks a Staff Engineer, Physical Design with 5+ years of experience. Must have expertise in ASIC design flow, Verilog HDL, chip synthesis, timing closure, and Synopsys/Cadence tools.  Experience with static timing analysis, EM/IR-Drop/Xtalk analysis, and formal/physical verification is a plus.

Marvell

<div class="css-ey7qxc"><div data-automation-id="jobPostingDescription" class="css-dwylkc">About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.&nbsp;At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.&nbsp;Your Team, Your ImpactMarvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production.What You Can ExpectAs member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, to physical verification (DRC/LVS/Antenna). You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tape-outs.What We're Looking For<ul><li>BS/MS in EE/CS with 5+ years and be familiar with physical design methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, chip synthesis and timing closure.</li><li>Must be programming-minded, write makefile/Tcl/Perl to automate design process and improve efficiency.</li><li>Detail oriented, self-motivated team worker, good verbal and written communication skills.</li><li>Familiar with Synopsys suite (IC Compiler, Fusion Compiler), Cadence suite (Innovus).</li><li>Knowledge on static timing analysis (PrimeTime), EM/IR-Drop/Xtalk analysis (Celtic, PT-SI, Apache, AstroRail, PrimeRail), formal or physical verification (Formality, Verplex/LEC, Calibre, Hercules) a plus.</li></ul><h3></h3>Additional Compensation and Benefit ElementsWith competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our <a rel="noopener noreferrer" target="_blank" href="https://www.marvell.com/company/careers/">Careers</a> page.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.#LI-TN2</div></div>