Infineon is seeking a Staff SOC Engineer with at least 5 years of experience in physical design for complex SoCs.  Must have expertise in Synthesis, Place & Route, Timing Closure, and FINFET technologies.  Experience in scripting languages like Tcl, Perl, or Python is essential.  Join a global leader in semiconductor solutions for green and efficient energy, clean and safe mobility, and smart and secure IoT.

Semiconductors are crucial to solve the energy challenges of our time and shape the digital transformation. This is why Infineon is committed to actively driving decarbonization and digitalization. As a global semiconductor leader in power systems and IoT, we enable game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. We make life easier, safer, and greener. Together with our customers and partners. For a better tomorrow.With a unique team, employees from more than 90 countries make Infineon a successful international company – with their skills, their enthusiasm and the courage to challenge the status quo and open up new horizons. Since the semiconductor was invented, we have helped shape the future – every single day.

Infineon Technologies

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 In your new role you will: <ul><li>Contribute to highly complex designs in a multi-site organization covering all aspects of Structural and Physical SoC Design</li><li>Be responsible for the physical design of multifarious digital SoCs</li><li>Translate requirements into layout specifics using our state-of-the-art EDA tools and flows</li><li>Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis and equivalence check, generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and Physical Sign off including Power Integrity</li><li>Take physical limitation of hierarchical deep sub-micron designs into account and timely implement suitable solutions to overcome implementation issues.</li><li>Tap your experience to contribute significantly to the development and implementation of clocking architectures</li><li>Be a member of an expert network and participate to drive innovation, methodology and flow topics in the SoC Floorplanning and Top-Level Timing Closure domain for next generation SoCs </li></ul>
You are best equipped for this task if you have: <ul><li>A degree in Electrical Engineering, Microelectronics or a similar field</li><li>At least 5 years of working experience in Physical Design handling highly complex SoCs - with sound experience in Synthesis, Place &amp; Route and Timing Closure and involvement in FINFET technologies</li><li>Know-how in technical leadership in physical design projects</li><li>Sound programming skills and knowledge in scripting languages like Tcl, Perl or Python</li><li>Basic experience in RTL coding</li><li>Understanding of Functional Safety will be a benefit</li><li>Fluent English language skills – with German being an added plus </li></ul>
#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity &amp; Inclusion at Infineon.
 
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