Staff Verification Engineer
8 Minutes ago • 4 Years +
Quality Assurance
Job Description
Semtech is seeking a Staff Verification Engineer to perform block and chip-level verification using RTL, gate-level, and analog/mixed-signal simulations. The role involves developing verification strategies, creating tests, running regressions, and monitoring coverage to ensure tape-out quality. The engineer will also support post-silicon debug and improve verification scalability through environment enhancements and tool automation. This position requires strong System Verilog, UVM, and scripting skills.
Good To Have:
- Experience setting up UVM verification environment from scratch.
- Familiarity with VHDL or System Verilog RNM.
- Automation of verification flow with Python/Perl in industrial setting.
- Analog behavioral model development/verification experience.
Must Have:
- Perform block and chip-level verification in RTL, gate-level, and AMS.
- Run digital/mixed-signal simulations and formal verification.
- Develop tests, run regressions, and monitor coverage for tape-out quality.
- 4+ years experience in semiconductor industry.
- M.S. in EE/CS/CE or higher.
- Hands-on experience with System Verilog and UVM implementation.
- Debugging digital simulation in both RTL and gate-level netlist.
- Scripting experience in Python or Perl.
- Clear understanding of ASIC design flow.
- Solid analytical and problem-solving skills.
- Excellent verbal and written communication skills.
Responsibilities:
- Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).
- Run digital/mixed-signal simulations as well as formal verification.
- Work closely with the design team to create verification strategy and detailed verification plan.
- Develop tests, run regressions and monitor coverage to ensure tape-out quality.
- Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
- Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.
- Improve verification scalability and portability from project to project by environment enhancement and tools automation.
Minimum Qualifications:
- 4+ years experience in semiconductor industry
- M.S. in EE/CS/CE or higher
- Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
- Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
- Scripting experience in Python or Perl.
- Clear understanding of ASIC design flow
- Solid analytical and problem solving skills
- Independent, self-motivated, rigorous, team player and able to follow through
- Excellent verbal and written communication skills
Desired Qualifications
- Experience of setting up UVM verification environment from scratch
- Familiarity with VHDL or System Verilog RNM
- Automation of verification flow with Python/Perl in industrial setting
- Analog behavioral model development/verification experience
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