Stage Ingénieur : Amélioration de la robustesse et Automatisation de la Vérification des Transitions F/M

7 Months ago • All levels • Marketing

Job Details

Contexte

NXP Semiconductors est un des leaders mondiaux dans le développement et la fabrication de produits semiconducteurs et participe activement dans l’innovation des applications embarquées pour les marchés de l'automobile, des objets connectés, du grand public, de l'industriel et des communications.

L’équipe MCU/MPU Engineering (MME), basée à Grenoble, participe à la conception des circuits i.MX de NXP. Elle a la charge du développement de l’architecture à la finalisation des tests pour la mise en production.

Le stage d’une durée de 6 mois, vous permettra d’intégrer l’équipe de conception pour contribuer activement à l’amélioration de l’efficacité du flot de conception.

Les communications entre domaines d'horloge asynchrones (CDC) peuvent introduire des bugs critiques dans les designs, rendant essentielle la réalisation d'analyses approfondies pour prévenir d'éventuels échecs en silicium. Ce processus repose souvent sur des hypothèses spécifiques dérivées des spécifications technique. Cependant, si l'une de ces hypothèses s'avère incorrecte, cela peut entraîner des bugs non détectés dans le produit final.

L'objectif de ce stage est d'évaluer les fonctionnalités des outils de vérification qui peuvent confirmer la validité de ces hypothèses dans un environnement de vérification fonctionnelle. En participant à ce projet, vous acquerrez une expérience pratique dans l'identification et l'atténuation des problèmes liés aux CDC, garantissant ainsi l'intégrité de la conception.

Nous recrutons un stagiaire de fin d’étude sur une durée de 6 mois.

Vos missions

Le(a) stagiaire prendra en charge/réalisera une ou plusieurs des missions suivantes :

1. Apprentissage et compréhension des problématiques liées aux CDC

2. Analyse des différentes fonctionnalités des outils pour améliorer la qualité des résultats

3. Mise en place de solution pour évaluer ces fonctionnalités sur des cas concrets

4. Développer une méthode pour appliquer la solution sur de futurs projets

Votre profil

  • Bac +5, dernière année d’école d’ingénieur ou Master II en micro-électronique.
  • Connaissance du processus de conception des circuits intégrés.
  • La connaissance de l’activité de synthèse est un plus.
  • Bon niveau d’anglais exigé.

Context

NXP Semiconductors is a global leader in the design and manufacturing of semiconductor products and is actively involved in the innovation of embedded applications for the automotive, wearable, consumer, industrial and communications markets.

The MCU/MPU Engineering (MME) team, based in Grenoble, participates in the design of NXP's i.MX circuits. Our organization is in charge of the development of the architecture until the finalization of the tests for the production.

The 6-month internship will allow you to join the design team to actively contribute to improving the efficiency of the design flow.

Asynchronous Clock Domain Crossing (CDC) communications can introduce critical bugs in designs, making thorough analysis essential to prevent potential silicon failures. This process often relies on specific assumptions derived from technical specifications. However, if any of these assumptions turn out to be incorrect, it can lead to undetected bugs in the final product.

The objective of this internship is to evaluate the capabilities of verification tools that can confirm the validity of these assumptions in a functional verification environment. By participating in this project, you will gain hands-on experience in identifying and mitigating issues related to CDC, thereby ensuring the integrity of the design.

We are looking for an intern for six months.

Your responsibilities

The trainee will be responsible for/perform one or more of the following tasks :

Learning and understanding the issues related to CDC. Analyzing the different features of tools to improve the quality of results. Implementing solutions to evaluate these features on concrete cases. Developing a method to apply the solution to future projects.

Your profile

  • Education level :  Master Degree / last year of engineering school in

Knowledge required in:

  • Knowledge of integrated circuit design process.
  • Knowledge of synthesis activity is a plus.
  • A good level of English is required, working in an international multi-site team.

Project plan

The proposed plan for this project is the following:

Gain a comprehensive understanding of the general concepts and design techniques related to digital Clock Domain Crossing (CDC). Explore the clock domain strategy specific to the iMX9 architecture. Focus on the various mixes within the iMX9 platform. Investigate the MME CDC policy. Study the RTL design flow in MME, ensuring a clear understanding of the purpose and significance of each step. Set up the DISPLAYMIX environment. Identify areas for improvement, which will be the primary focus of this internship: evaluating tool features and engaging in weekly discussions with the Field Application Engineer (FAE). Analyze different tool feature options (protocol checkers) and implement them in our design projects. Utilize a functional verification environment to assess and draw conclusions from the tool results. Work with the Questa CDC tool:

Configure the tool for optimal performance.

Interpret the results of structural analysis.

Set up protocol checkers to ensure compliance.

Integrate the tool into the functional verification environment.

Investigate and analyze the results obtained.

More information about NXP in France...

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