Static Timing Analysis Engineer, FullChip/ASIC Implementation

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of technical experience in silicon timing closure and chip integration.
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
• Experience with high complexity silicon in state-of-the-art technology process nodes.
• Experience with ASIC design flows and methodology of static timing analysis.
• Effective skills with scripting languages such as Tcl or Perl.