ISCP MIP MYS is seeking candidate for the role of Structural Design Engineer to join our talented and vibrant team. You will be directly involved in delivering next-generation high speed PHY designs for SoC applications on Ieading process nodeKey Responsibilities for this position includes but not limited to:
Working closely with Architecture and Design team to understand, define and generate timing specification/clocking/constraints/extractions/ptpx
Drive Implementation requirements (for example, Clock Tree Synthesis targets), Influence and Continuous seek to improve the Timing Closure methodology, etc
Drive timing closure, execute STA using industry tool (Primetime) and perform various quality check to ensure design converges on the timing signoff requirements.
Analyze timing report and proficient in using script to debug, automate tasks and provide timely feedback for timing ECO.
Define and develop I/O budgets and drive for IP budget convergence.
You should possess a relevant educational qualification, BSEE or equivalent with 4+ years/MSEE or equivalent with 3+ years design experience in the structural/physical design domain. Additional qualifications include:
Have multiple tape-out experience in deep submicron process nodes
Must have in depth, extensive knowledge and hands-on experience in Static timing analysis and timing signoff, including SDC development and timing budgeting.
Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage
Experienced in industry STA tools: Primetime and Primetime SI
Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL and Verilog.
Experience of mentoring junior team members and charting their development for success.
Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.
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