Turing Design Verification Sr Lead Engineer

4 Months ago • 5-8 Years

Software Development & Engineering

Job Description

The Senior Lead Engineer will be part of the team verifying advanced IPs, HW Accelerators, and Subsystems for AI/ML/DL Applications. The role involves functional, formal, power-aware, and gate-level simulation, working on the latest tech nodes. Responsibilities include test plan creation, coverage model development, test case writing, and coverage closure. The engineer will be working on IP verification and own various DV tasks. Exposure to the design and verification of the latest Qualcomm AI/ML/DL IPs/Cores. Debug experience is required.

Good To Have:

Understanding of digital signal processing concepts.
Experience with Machine Learning concepts and libraries.
Knowledge of MEMs & inertial sensors.
Experience in people management and mentoring.

Must Have:

Proficient in System-Verilog and scripting languages like Shell and Perl
RTL/gate level simulation debug experience
Working knowledge of bus protocols like AHB/AXI
Good in SV, UVM, Assertions, GLS
Solid knowledge of C and scripting languages like Python

Perks:

Salary, stock and performance related bonus
Maternity/Paternity Leave
Employee stock purchase scheme
Matching pension scheme
Education Assistance
Relocation and immigration support (if needed)
Life, Medical, Income and Travel Insurance
Subsidised memberships for physical and mental well-being
Bicycle purchase scheme
Employee run clubs

Add these skills to join the top 1% applicants for this job

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test-coverage

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Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications

Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core

Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation

Get to work on the latest and cutting-edge tech nodes

Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure.

Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience.
Should have a working knowledge of bus protocols like AHB/AXI .
Candidates should have 5-8 years experience.
Good in SV, UVM, Assertions, GLS
Solid knowledge of C and Scipting language like python
Working knowledge of bus protocol like AHB/AXI

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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