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AI/ML RTL Design Engineer, TPU, Google Cloud

Karnataka, India (On-site)

AI/ML RTL Design Engineer, TPU, Google Cloud

1 Month ago • 3 Years + • Research & Development • Undisclosed

About the job

6 skills required for this role

Add these skills to join the top 1% applicants for this job

neural-networks

cpp

python

perl

fpga

innovation

Job Description

This role involves designing and implementing AI/ML hardware acceleration for Google's TPUs. Responsibilities include RTL implementation, quality checks, collaboration with other teams (DV, Physical Design), power/performance optimization, and participation in synthesis and silicon bring-up. The engineer will work on complex digital designs within the TPU architecture and its integration into AI/ML systems. The work focuses on developing System-on-a-chip (SoC) for machine learning acceleration in data centers, solving technical problems with innovative logic solutions, and evaluating design options based on complexity, performance, power, and area.

Must have:

Bachelor's degree in relevant field
3+ years ASIC/SoC development (Verilog/SystemVerilog)
ML/Graphics IP design experience
ASIC design verification, synthesis, timing/power analysis, DFT
RTL implementation and quality checks

Good to have:

Python, C/C++, Perl programming
SoC design and integration
High-performance/low-power design
Neural networks, arithmetic units, processor design knowledge

Minimum qualifications:

Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
3 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
Experience in design of Machine Learning IPs, or graphics IPs, managing low precision/mixed precision numerics.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

Experience with programming languages (e.g., Python, C/C++ or Perl).
Experience in SoC designs and integration flows.
Knowledge of high performance and low power design techniques
Knowledge of neural networks, arithmetic units, processor design, accelerators, bus architectures or memory hierarchies.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be part of a team developing System-on-a-chip (SoC) used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver high quality designs for next generation data center accelerators.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Participate in implementation of AI/ML Compute intensive IPs and subsystems.
Take ownership of Register-Transfer Level (RTL) implementation and quality checks of one or more modules.
Contribute to design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.
Identify and drive power, performance and area improvements for the modules owned.
Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.

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Google

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