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Design Engineer II

Karnataka, India (On-site)

Design Engineer II

2 Months ago • 1-4 Years • Research & Development

About the job

5 skills required for this role

Test your skills to join the top 1% applicants for this job

cpp

prototyping

python

fpga

testing

Job Description

Cadence seeks a Design Engineer II with 1-4 years of experience in Post-Silicon Physical Layer Electrical Validation, specializing in high-speed SERDES protocols like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO. Hands-on experience with lab equipment (oscilloscopes, network analyzers, BERTs) is essential.

Must have:

Post-Silicon Validation
High-speed SERDES
Lab Equipment
Physical Layer

Good to have:

Team Management
FPGA Design
Pre-Silicon Validation
Verilog RTL

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Minimum Qualifications:

2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation

Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc

Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc

Preferred Qualifications:

Experience managing small teams (at least 2 members and above)

Experience leading the complete post silicon validation efforts for at least one full project

1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping

Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.

Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL

Experience conducting hiring interviews and mentoring new hires

BE/BTech/ME/MTech or equivalent