Fabric/Interconnect Architect

2 Months ago • All levels • Research & Development • Undisclosed

About the job

2 skills required for this role

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cpp

python

Job Description

Our mission is to create computing platforms (HW/SW co-design) that will transform the industry with the most advanced technologies. As fabric architect, you will be responsible for the internal interconnect architecture specification and its performance, power, area requirements. This will cover both coherent and non-coherent interconnects and chiplet-to-chiplet connections. You will be working with the Silicon team (eg. RTL/microarchitecture, DV, PD, Perf, DFT) members and industry consortiums such as UCIe.

Requirements

Thorough knowledge of large scale on-chip fabric or on-chip interconnect architecture
Knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB.
Knowledge of cache coherent memory systems and interconnect.
Familiarity with different on-chip network topologies (ring, mesh, xbar etc).
Knowledge of SystemVerilog or Verilog, C or C++, scripting languages such as Python
Experience with functional and performance simulators
Knowledge of logic design principles along with timing and power implications
Understanding of low power architecture techniques
Understanding of high performance techniques and trade-offs in fabric architecture

Responsibilities

Architecture development and specification - from early high-level architectural exploration through micro architectural direction and writing a detailed specification
Coherent and non-coherent interconnects within the chip, coherency protocol, directory structure, bandwidth and latency targets
Development, assessment, and refinement of Architecture to target power, performance, area, and timing goals
Helping produce and review validation plans for functionality and performance

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