Lead Education Application Engineer

3 Months ago • 4-6 Years • Education • Undisclosed

About the job

Job Description

Lead Education Application Engineer at Cadence. Must have experience in mixed-signal design and verification flows, analog/mixed-signal circuits, Verilog-A/AMS, and Cadence design tools like Virtuoso, AMS Designer, and Spectre. Strong communication skills are required.
Must have:
  • Mixed-signal design
  • Analog/mixed-signal circuits
  • Verilog-A/AMS modeling
  • Cadence design tools
Good to have:
  • SystemVerilog/real-number modeling
  • UVM-MS
  • Low-power mixed-signal
  • CPF/UPF
Perks:
  • One Cadence culture
  • Impactful work

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

•             Working with product engineers, customer support, and R&D to determine training requirements.

•             Creating and updating training lectures, labs, exams, and demos aligned with software releases and with high levels of quality.

•             Designing and developing lectures, labs, and demos deployed online and in the classroom.

•             Delivering courses in a classroom or virtual setting

•             Creating narrated online videos educating customers on how to use tools, languages, and methodologies.

•             Supporting online training customers when there are questions related to lectures and labs.

•             Enjoys various activities – authoring content, learning new tools and methodologies, “being the expert,” teaching and interacting with customers, and working with highly competent and experienced engineers.

•             Given clear goals, can work independently to accomplish such goals.

•             Is aware of mixed-signal design and verification flows and methodologies.

•             Has experience in designing and analyzing analog and mixed-signal circuits.

•             Can model and create test benches for mixed-signal, mixed-language designs using Verilog-A and Verilog-AMS.

•             Should be able to model DUT and testbench for Top Level Verification of mixed-signal designs.

•             Has working knowledge of analog/mixed-signal Cadence design tools and simulators such as Virtuoso, AMS Designer, and Spectre.

•             Has hands-on experience with SystemVerilog/real-number modeling capabilities (SVRNM/Wreal), and UVM-MS would be a plus.

•             Is aware of low-power mixed-signal design requirements with CPF and UPF.

•             Should have a Bachelors’ or Master's degree in Electrical/Electronics Engineering with a minimum 4-6 years of related working experience.

•             Has strong written and verbal English communication skills.

Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.

We’re doing work that matters. Help us solve what others can’t.

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San Jose, California, United States (On-Site)

Bengaluru, Karnataka, India (On-Site)

Bengaluru, Karnataka, India (On-Site)

Shanghai, Shanghai, China (On-Site)

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