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Logic MicroArchitect:

Karnataka, India (Hybrid)

Logic MicroArchitect:

3 Months ago • 12-15 Years • Research & Development • Undisclosed

About the job

3 skills required for this role

Add these skills to join the top 1% applicants for this job

communication

data-driven-decisions

cross-functional

Job Description

Lead the development of high-speed SerDes design. As the lead of micro-architectural definition and design implementation, drive logic chip design achieving data of 16Gbs and above. Must have Serdes experience, mixed-signal IP experience, proficiency in Verilog and VHDL, and experience with SoC design methodologies.

Must have:

Serdes experience
Mixed-signal IP
Verilog, VHDL
SoC design

Good to have:

SoC Microarchitecture
Processor design
PCIE G3/G4/G5
MIPI CSI/DPHY

Perks:

Automotive space
Fun work environment

About the job

Logic MicroArchitect:

Location: Bangalore

We are looking for someone who will lead the development of high-speed cutting-edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above.

SoC Micro-Architect, you will play a key role in the design and development of complex ASICs and System-on-Chip architectures for various electronic devices. You will be responsible for defining the microarchitecture of the SoC, optimizing performance, power efficiency, and area constraints while ensuring compatibility with system-level requirements. You will also need to define and validate analog-digital interfaces.

Qualifications:

Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.

Serdes experience and mixed-signal IP experience is a must.

Solid understanding of computer architecture principles, including CPU, GPU, memory hierarchy, and interconnect architectures.

Proficiency in hardware description languages (Verilog, VHDL) and microarchitecture modeling tools (SystemVerilog, SystemC).

Experience with SoC design methodologies, including RTL design, synthesis, timing analysis, and physical design.

Strong analytical and problem-solving skills, with the ability to analyze complex system-level trade-offs and make data-driven decisions.

Excellent communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams in a dynamic environment.

Prior experience in SoC microarchitecture design, processor design, or related fields is a plus.

Experience:

12+ Years of experience in PCIE G3/G4/G5 or MIPI CSI/DPHY and Display Port.

Must be familiar with the PHY Logic design challenges