Job Description
The Principal Application Engineer will work closely with the sales team to identify and scope opportunities for the Cadence functional logic verification platform. They will understand the goals and objectives, plan, execute, and manage key technical evaluations by collaborating with existing and potential customers and team members. The role involves summarizing tasks and projects, reporting to managers, training and supporting customer projects, conducting training and presentations, and ramping up team members on advanced verification technologies and tools. They will also provide technical expertise to address client queries.
Good To Have:
- Knowledge of Metric Driven Verification (MDV) using vManager CS
- Experience optimizing RTL and Gate-level simulation using profiling tools
Must Have:
- BS in CS or EE with 10+ years of industry experience
- 10+ years hands-on hardware design & verification expertise
- Experience using HDL simulators (e.g., ies, vcs, or questa)
- Verification experience using systemVerilog/Verilog/VHDL/SystemC
- Experience with UVM methodology or similar
- Hands-on Design experience using SystemVerilog, Verilog and VHDL
- Knowledge of VIPs and code & functional coverage tools (IMC preferred)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Work closely with the sales team to identify and scope opportunities for the Cadence functional logic verification platform
- Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
- Summarize the tasks and projects, and report to manager and share with team effectively
- Train, ramp-up and accompany customer project.
- Conduct basic and advanced trainings, presentations and demos as necessary.
- Ramp-up other members of the team on the advanced verification technologies and tools.
- Providing technical expertise to address clients’ queries, which need expert involvement
Requirement
- The candidate should possess minimum BS level of CS or EE with 10+ years of industry experience.
- Minimum 10+ years hands-on, high expertise on hardware design & verification techniques.
- Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.
- Hands on Verification experience using systemVerilog/Verilog/VHDL/SystemC.
- Experience on UVM methodology or similar one should be preferred.
- Hands-on Design experience using SystemVerilog, Verilog and VHDL. - Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies. - Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.
- Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.
- Good communication skills in English and a strong desire for working in a global environment with customers and BU people.
- Current passport is required with no travel limitations
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