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Principal Design Engineer

Karnataka, India (On-site)

Principal Design Engineer

3 Months ago • 6 Years + • Research & Development • Undisclosed

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Job Description

Cadence seeks a Principal Design Engineer with 6+ years of experience in custom layout, particularly FinFET technology layouts for 3nm/5nm and 7nm nodes. Experience with high-speed analog mixed-signal layout is desirable. The role involves leading Memory PHY layout design, performing hands-on design of critical analog and high-speed layout blocks, and coordinating with circuit leads and layout teams.

Must have:

Custom Layout
Finfet Technology
3nm/5nm/7nm Nodes
High-Speed Analog

Good to have:

Mixed-Signal Layout
Memory PHY Layout
Circuit Design
Layout Reviews

Perks:

Leadership Opportunities
Impactful Technology

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Candidate should have worked on Finfet technology layouts. Exposure to technology nodes like 3nm/5nm and 7nm is required.

Candidate should have 6+ years of experience in custom layout. Experience on high-speed analog mixed-signal layout is desirable.

Role:

Candidate will own and Lead Major blocks of Memory PHY Layout design.
Candidate would perform hand-on design of critical analog and high-speed layout blocks.
Candidate would co-ordinate design work with Circuit leads, layout contractors and layout team members.
Candidate would participate in layout reviews by presenting and reviewing custom layout designs.