RTL Design Engineer
Job Summary
Job Description
- PhD in relevant field
- RTL coding and Verilog/SystemVerilog experience
- Develop SystemVerilog RTL
- Work with cross-functional teams
- Design verification and debugging
- Digital clock control circuits experience
- Scripting language (Python/Perl)
- Processor/accelerator knowledge
- High-performance/low-power design
- Bonus
- Equity
- Benefits
4 skills required
Job Details
Minimum qualifications:
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Academic, educational, internship, or project experience with RTL coding and Verilog/SystemVerilog.
Preferred qualifications:
- Experience with digital clock control circuits.
- Experience interacting with software, architecture, and other cross-functional teams.
- Experience with a scripting language (e.g., Python or Perl)
- Knowledge of processor design or accelerators.
- Knowledge of high-performance and low power design techniques.
About the job
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Work mostly independently to create and review clock control subsystem's design microarchitecture specifications.
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
- Work with architecture and power teams to evaluate features and their impact.
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
- Work with physical design teams to ensure design meets physical requirements and timing closure.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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