RTL design verification /ASIC design verification
1 Year ago โข 3-7 Years โข โน1,00,000 LPA - โน2,00,000 LPA
Research Development
Job Description
RTL design verification engineer needed with 3+ years of experience in Verilog/SystemVerilog and proficiency in UVM/OVM. Strong understanding of ASIC design flow and verification techniques are essential. This role contributes to the development of verification plans for complex RTL designs.
Good To Have:
- Formal Verification
- Scripting Languages
- Industry Protocols
- AXI/AHB
Must Have:
- Verilog/SystemVerilog
- UVM/OVM
- ASIC Design
- Verification Techniques
Perks:
- Professional Growth
- Collaborative Culture
About the job
Ti๐๐๐จ๐ข๐ง ๐๐ฎ๐ซ ๐๐๐๐ฆ ๐๐ฌ ๐๐ง ๐๐๐ ๐๐๐ฌ๐ข๐ ๐ง ๐๐๐ซ๐ข๐๐ข๐๐๐ญ๐ข๐จ๐ง ๐๐ง๐ ๐ข๐ง๐๐๐ซ! at ARF Design๐
Are you passionate about #RTL_Design_verification? We're seeking a talented engineer to join our team and contribute to the semiconductor industry.
๐๐จ๐ฌ๐ข๐ญ๐ข๐จ๐ง: #RTL_Design_Verification_Engineer
๐ผ๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐: 7+ Years
๐๐จ๐๐๐ญ๐ข๐จ๐ง: #Bangalore #Bhubaneswar #hyderabad
๐๐๐ฌ๐ฉ๐จ๐ง๐ฌ๐ข๐๐ข๐ฅ๐ข๐ญ๐ข๐๐ฌ::
โถDevelop and execute verification plans for complex RTL designs.
โถPerform functional and performance verification of design blocks.
โถCollaborate with cross-functional teams to ensure successful IP component integration.
โถContribute to enhancing verification methodologies and best practices.
๐๐ฎ๐๐ฅ๐ข๐๐ข๐๐๐ญ๐ข๐จ๐ง๐ฌ:
Bachelor's or Master's degree in Electrical Engineering/Electronics & Communication Engineering or related field.
๐๐๐ซ๐ข๐ฆ๐๐ซ๐ฒ ๐๐๐ช๐ฎ๐ข๐ซ๐๐ฆ๐๐ง๐ญ๐ฌ::
โถMinimum of 3+ years of experience in RTL design verification.
โถProficiency in Verilog/ SystemVerilog and experience with industry-standard verification methodologies (OVM/UVM).
โถStrong understanding of ASIC design flow and verification techniques.
โถExcellent problem-solving and debugging skills.
๐๐๐๐๐จ๐ง๐๐๐ซ๐ฒ ๐๐๐ช๐ฎ๐ข๐ซ๐๐ฆ๐๐ง๐ญ๐ฌ:
โถExperience with formal verification tools and methodologies.
โถFamiliarity with scripting languages (e.g., Python, Perl) for automation tasks.
โถKnowledge of industry-standard protocols and interfaces (e.g., PCIe, AXI, AHB).
๐๐๐ง๐๐๐ข๐ญ๐ฌ:
โOpportunities for professional growth and career advancement.
โVibrant and inclusive work culture that values collaboration and innovation.
๐๐๐๐๐ฒ ๐ญ๐จ ๐๐จ๐ข๐ง ๐๐ฌ?
If you're ready to take your career to the next level and contribute to groundbreaking projects, we want to hear from you!
๐๐ฅ๐๐๐ฌ๐ ๐ฌ๐ฎ๐๐ฆ๐ข๐ญ ๐ฒ๐จ๐ฎ๐ซ ๐ซ๐๐ฌ๐ฎ๐ฆ๐/๐๐ ๐ญ๐จ ๐poojakarve@arf-design.com
๐๐จ๐ญ๐: Please name the file in the following format: Your Full
๐๐๐ฆ๐_ ๐๐๐ฌ๐ข๐ ๐ง๐๐ญ๐ข๐จ๐ง_ ๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐.
#RTLDesign #VerificationEngineer #Semiconductor #TechJobs #EngineeringCareers #JoinOurTeam #Innovation #immediatejoiners #hiring #wfojobs #fulltimeemploymentps: Provide a summary of the role, what success in the position looks like, and how this role fits into the organization overall.
Skills: design,rtl design,asic design,semiconductor,universal verification methodology (uvm),verilog,systemverilog
Are you passionate about #RTL_Design_verification? We're seeking a talented engineer to join our team and contribute to the semiconductor industry.
๐๐จ๐ฌ๐ข๐ญ๐ข๐จ๐ง: #RTL_Design_Verification_Engineer
๐ผ๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐: 7+ Years
๐๐จ๐๐๐ญ๐ข๐จ๐ง: #Bangalore #Bhubaneswar #hyderabad
๐๐๐ฌ๐ฉ๐จ๐ง๐ฌ๐ข๐๐ข๐ฅ๐ข๐ญ๐ข๐๐ฌ::
โถDevelop and execute verification plans for complex RTL designs.
โถPerform functional and performance verification of design blocks.
โถCollaborate with cross-functional teams to ensure successful IP component integration.
โถContribute to enhancing verification methodologies and best practices.
๐๐ฎ๐๐ฅ๐ข๐๐ข๐๐๐ญ๐ข๐จ๐ง๐ฌ:
Bachelor's or Master's degree in Electrical Engineering/Electronics & Communication Engineering or related field.
๐๐๐ซ๐ข๐ฆ๐๐ซ๐ฒ ๐๐๐ช๐ฎ๐ข๐ซ๐๐ฆ๐๐ง๐ญ๐ฌ::
โถMinimum of 3+ years of experience in RTL design verification.
โถProficiency in Verilog/ SystemVerilog and experience with industry-standard verification methodologies (OVM/UVM).
โถStrong understanding of ASIC design flow and verification techniques.
โถExcellent problem-solving and debugging skills.
๐๐๐๐๐จ๐ง๐๐๐ซ๐ฒ ๐๐๐ช๐ฎ๐ข๐ซ๐๐ฆ๐๐ง๐ญ๐ฌ:
โถExperience with formal verification tools and methodologies.
โถFamiliarity with scripting languages (e.g., Python, Perl) for automation tasks.
โถKnowledge of industry-standard protocols and interfaces (e.g., PCIe, AXI, AHB).
๐๐๐ง๐๐๐ข๐ญ๐ฌ:
โOpportunities for professional growth and career advancement.
โVibrant and inclusive work culture that values collaboration and innovation.
๐๐๐๐๐ฒ ๐ญ๐จ ๐๐จ๐ข๐ง ๐๐ฌ?
If you're ready to take your career to the next level and contribute to groundbreaking projects, we want to hear from you!
๐๐ฅ๐๐๐ฌ๐ ๐ฌ๐ฎ๐๐ฆ๐ข๐ญ ๐ฒ๐จ๐ฎ๐ซ ๐ซ๐๐ฌ๐ฎ๐ฆ๐/๐๐ ๐ญ๐จ ๐poojakarve@arf-design.com
๐๐จ๐ญ๐: Please name the file in the following format: Your Full
๐๐๐ฆ๐_ ๐๐๐ฌ๐ข๐ ๐ง๐๐ญ๐ข๐จ๐ง_ ๐๐ฑ๐ฉ๐๐ซ๐ข๐๐ง๐๐.
#RTLDesign #VerificationEngineer #Semiconductor #TechJobs #EngineeringCareers #JoinOurTeam #Innovation #immediatejoiners #hiring #wfojobs #fulltimeemploymentps: Provide a summary of the role, what success in the position looks like, and how this role fits into the organization overall.
Skills: design,rtl design,asic design,semiconductor,universal verification methodology (uvm),verilog,systemverilog
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