Silicon CAD EDA Methodology Lead, TPU Google Cloud

9 Months ago • 14 Years +

Research Development

Job Description

This role involves leading the development and implementation of AI/ML-enhanced chip design methodologies within Google's TPU team. Responsibilities include partnering with cross-functional teams, proposing and implementing software automation to improve ASIC and SoC EDA flows, performing tool evaluations, and leading the creation of internal software tools. The ideal candidate will have extensive experience in ASIC chip design, EDA tools, and programming (Python/C++), and a strong understanding of chip design processes. They will drive process improvement projects, collaborate on strategic opportunities, and work directly with hardware teams to deploy tools impacting Google's chip hardware development.

Good To Have:

AI/ML experience in ASIC development
Experience deploying new tools and flows
Knowledge of physical design, floorplanning, sign-off
Excellent presentation skills

Must Have:

14+ years ASIC Chip Design experience
8+ years EDA tool experience
Python/C++ programming proficiency
Strong software skills
Lead end-to-end projects

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cpp

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Minimum qualifications:

Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
14 years of experience working in the ASIC Chip Design team, with 8 years of experience in hardware electronic design automation tools.
Experience programming in Python/C++.
Experience in writing code and design practices.

Preferred qualifications:

Experience in AI/ML methods for ASIC development.
Experience planning and deploying new tools and flows to users.
Knowledge of chip design processes such as physical design, floorplanning, and sign-off.
Ability to present and explain novel methods to users.
Strong programming/software skills like C/C++/Python.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will help deliver products that have a substantive impact on the Technical Infrastructure. You will provide leadership in an innovative and fast-paced environment with a focus on infrastructure for chip design. You'll also lead technical projects from the concept/planning stage through execution and closure. You will enable the wider team to deliver designs of different application areas, including ML/AI acceleration by developing tools relying on AI/ML techniques. You will lead end-to-end chip design process improvement projects

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

Partner cross-functionally to incorporate AI/ML techniques in chip design methodology and integrate into development flow.
Partner with teams to influence and standardize methodology across projects and functional areas (e.g., Design, Verification, Emulation, and other front end domain).
Propose, design, and implement software automation addressing bottlenecks in today's ASIC and SoC EDA flow. Perform or guide technical evaluations of tools and their AI capabilities and drive planning for possible deployment.
Lead the development of internal software tools and automation efforts, participate in design reviews, and engage in influencing and scheduling trade-off discussions. Collaborate to identify and create strategic opportunities for improved chip design across Google.
Work directly with a hardware team on projects-prototype and deploy tools to make a positive impact on Google's chip hardware development process.