Staff Engineer - SOC RTL Design

The Opportunity

We're looking for the Wavemakers of tomorrow.

[Company Name] is expanding its team in Chiplet Architecture and Design! We are looking for talented RTL Design Engineers to contribute to our next generation Chiplet designs. This is an incredible opportunity to be part of the AI revolution and engage in the complete ASIC development cycle, from concept to product.

As an RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout.

What You'll Do:

• Micro architect and RTL Design of SoC SubSystem/IP blocks
• Will develop UPF and run CLP checks
• Will be responsible for RTL quality checks - Lint/CDC/LEC
• Create appropriate documentation for hardware blocks.
• Responsible for analyse / debug / fixing issues reported by verification team
• Will develop the synthesis constraints for the blocks / subsystem
• Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation

What You'll Need:

• Education: Bachelor's or master's degree in electrical or Electronics and Communication or Computer Science Engineering.
• Experience: 8+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs.
• Expertise:
• Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure.
• Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks.
• Ability to drive project milestones across design, verification, and physical implementation phases.
• Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable.
• Skills:
• Excellent communication and interpersonal skills.
• Ability to collaborate in a fast-paced, product-oriented, and distributed team environment.
• Minimum Qualifications:
• SoC Design Experience: Minimum 8+ years of hands-on experience in SoC design.
• Architecture Development: Ability to develop architecture and micro-architecture based on specifications.
• Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.
• Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage.
• Chip IO Design: Knowledge of chip IO design and packaging is beneficial.
• Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics.
• Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC.
• Timing Closure: Comprehensive understanding of timing closure is mandatory.
• Post-Silicon Debug: Experience in post-silicon bring-up and debugging.
• Decision Making: Ability to make effective decisions under incomplete information.
• Communication & Leadership: Strong leadership and communication skills to ensure effective program execution.

"Hybrid work environment"

As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:

• Great compensation package
• Restricted Stock Units (RSUs)
• Hybrid Working Model
• Provisions to pursue advanced education from Premium Institute, eLearning content providers
• Medical Insurance and a cohort of Wellness Benefits
• Educational Assistance
• Advance Loan Assistance
• Office lunch & Snacks Facility