Summer Intern - Mixed Signal Modeling & Verification Engineer

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

We are seeking a creative and hardworking engineering intern to join our outstanding Analog/Mixed-Signal Verification, Modeling and Methodology Team. You will collaborate with systems and design teams to facilitate tops down design methodology through the development and validation of System Verilog (SV) models. You will also work with chip and DV leads to plan, setup, & execute AMS/UVM verification. Additionally, we are seeking innovative individuals who are interested in this position which will play a vital role streamlining development methodology for our organization. We are proud of our exceptional environment and multi-faceted culture. Join us and be part of our journey, innovating incredible technology on a global basis!

As an intern, you’ll collaborate with experienced engineers to solve real-world challenges, contribute to product development, and gain hands-on experience in a fast-paced, supportive environment. This internship will take place during the Summer 2026 semester over the course of a 12-14 week long internship working a full-time schedule.

Responsibilities

• You will contribute to a team that performs verification planning and AMS simulation on full custom ASICs for audio processing applications
• Develop behavioral models using SystemVerilog real number modeling (sv-rnm), user-defined types(sv-udt), & Verilog AMS
• Independent Interpretation of analog circuit schematics into abstract models
• Performing regression debug support and other flow/infrastructure development

Required Skills and Qualifications

• Actively pursuing a Bachelors, Masters, or PhD in Electrical Engineering or Computer Engineering
• Good understanding of analog integrated circuit design
• Experience with System Verilog real number modeling (RNM) modeling and/or Verilog-A behavioral modeling
• Organized and detailed with strong communication skills
• Possess outstanding analytical and problem-solving skills
• Results-oriented and ability to operate in dynamic environment

Preferred Skills and Qualifications

• Python skills would be highly desirable

Cirrus Logic follows a 2+ day in-office work schedule but interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference. Interns must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning their internship with Cirrus Logic.

Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.