Analog Layout Design Summer 2026 Intern

The Cadence SSG Group custom layout team develops and delivers a variety of high-quality high-speed and high-accuracy CMOS integrated circuits IP for several foundries on their most advances nodes: finfet and gate all around nodes, 2nm and below. As part of Cadence, the Cadence IP group custom layout team not only enjoys access to unlimited licenses to all the current and novel Cadence layout and verification tools and features, we also participate in the development and validation of the Virtuoso and Pegasus improvements. Virtuoso is by far the most used layout editing tool in the industry.

As a custom layout intern, you will be involved in:

• Implementing high speed and high accuracy cells, blocks and IP blocks
• Working with seasoned and passionate custom layout designers from groups all over the world
• Working with experienced circuit designers from groups all over the world to understand their technical and schedule needs and how it would be best built in layout
• Collaborating with the Cadence R&D teams (Virtuoso, Pegasus, etc.) to help develop the layout editing and verification tools

Additional Job Description

• Pursuing BSEE, MSEE
• Exposure to microelectronics design and requirements
• Understanding of layout effects on the circuit such as speed, capacitance, power and area etc.,
• Knowledge of various analog layout techniques like matching, shielding etc.,
• Exposure to Cadence Virtuoso Layout and physical verification tools is a plus
• Team player, driven, self-motivated and autonomous
• Excellent communication, presentation and customer service skills