Job Description
Design and lead high-speed IP development, including USB3, PCIE, and DPHY. This role requires a strong individual contributor in the analog domain, participating in all development aspects: analog design, layout, digital design, documentation, and silicon validation. The position also involves customer-facing discussions.
Good To Have:
- Working experience in PHY (PCIE, USB2, USB3) development.
Must Have:
- Lead high-speed IP (USB3, PCIE, DPHY) development.
- Strong individual contributor in analog domain.
- Participate in analog design, layout, digital design, documentation, and silicon validation.
- Hands-on design experience in analog IP like PLLs, data converters, and serial interfaces.
- Participated in full cycles of analog IP creation from specification to silicon debug and characterization.
- Good communication skills and be a team player.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
B.Tech/BE/ME/Mtech
Job Description
Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development – analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions.
Requirements
B.Tech/BE/ME/Mtech
Exp - 5 +yrs
- Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc.
- Must have participated in full cycles of analog IP creation – right from spec to silicon debug and char
- Must have good communication skills and should be team player.
- Working experience in PHY (PCIE, USB2, USB3) development is desired
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