Design Engineer II - Verification

This role involves defining verification plans based on IP design specifications and leading a verification team to achieve coverage-driven verification goals. The Design Engineer II will be responsible for maintaining and developing verification test-benches, demonstrating a deep understanding of ASIC verification flow, and ensuring timely milestone delivery checks. The position requires an experienced professional in digital IC verification.

Must Have

• Define verification plan based on IP design SPEC.
• Lead verification team to achieve coverage driven verification goals.
• Maintain and develop Verification Test-Bench.
• Deep understanding of ASIC verification flow.
• Responsible for milestone delivery check.
• Master degree with 1+ years or bachelor with 2+ years as an experienced digital IC verification.
• Experienced in successful tape-out of ASIC chips.
• Familiar with UVM test-bench architecture.
• Experienced in test-bench development.
• Self-motivation with communication skills (spoken and written English and Mandarin).
• Experienced in coding of SV, Perl/Python, Makefile.

Position Description:

Specific duties include:

• Responsible for verification plan define based on IP design SPEC.
• Lead verification team to achieve the coverage driven verification goals.
• Verification Test-Bench maintain and development.
• Deep understanding on ASIC verification flow, responsible for milestone delivery check

Position Requirements:

• Master degree with 1+ years or bachelor with 2+ years as an experienced digital IC verification.
• Experienced in successful tape-out of ASIC chips
• Familiar to UVM test-bench architecture and experienced on test-bench development.
• Self-motivation with communication skills (spoken and written English and Mandarin)
• Experienced in coding of SV, Perl/Python, Makefile