ASIC Design&Verification Engineer Graduate (Video Silicon IP) - 2026 Start (BS/MS)

Responsibilities

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. We are looking for talented individuals to join our team in 2026. As a graduate, you will get opportunities to pursue bold ideas, tackle complex challenges, and unlock limitless growth. Launch your career where inspiration is infinite at ByteDance Successful candidates must be able to commit to an onboarding date by end of year 2026. Please state your availability and graduation date clearly in your resume. Candidates can apply to a maximum of two positions and will be considered for jobs in the order you apply. The application limit is applicable to ByteDance and its affiliates' jobs globally. Applications will be reviewed on a rolling basis - we encourage you to apply early. Responsibilities We are looking for both ASIC Front-end Design Engineers and Design Verification Engineers.

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification team to build high performance and low power video processing IPs. Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
• As a Design Verification engineer, you will be taking on an important role in helping deliver a Video Codec IP by generating test benches and running simulations. You will interface with architects and ASIC/FPGA design engineers to develop test plans, lead bug tracking, and automation of regression testing.

Qualifications

Minimum Qualifications

• Currently pursuing a PhD in computer science/electrical engineering or a related technical discipline
• Knowledge of Video Codecs
• Experience with RTL design (SystemVerilog) or High level Synthesis (HLS)
• Experience with UVM methodology, SystemC, or DPI
• Good programming skills in Python for task automation

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