CPU Power Engineer

Rivos is seeking highly motivated candidates for CPU power design, modeling, and optimization. The ideal candidate will possess in-depth experience in full-spectrum silicon power reduction, including solid power analysis, benchmarking, and design optimization at all levels (architecture, micro-architecture, implementation, and binning) for CPU blocks. Responsibilities include driving power design tasks across various teams, modeling use-cases and workloads, analyzing power-performance trade-offs, creating test vectors, performing power simulations and analysis, collaborating with CAD and physical design teams, and influencing SoC power. The role requires a strong understanding of CPU architectures, workload modeling, Verilog/SystemVerilog, silicon design flow, and EDA tools for power simulations.

Must Have

• 8-15 years CPU power design experience
• CPU architecture and workload modeling knowledge
• Experience with Verilog and SystemVerilog RTL
• Experience in silicon design flow and PPA tradeoffs
• Experience with EDA tools for power modeling/simulations
• Proficiency in Python, TCL, and scripting languages
• Ability to problem-solve and innovate under pressure

Good to Have

• RISC-V architecture familiarity
• Knowledge of device physics
• Experience with advanced process technology
• Circuit design fundamentals

• Drive the task of power design for CPU blocks across different teams including Arch, uArch, implementation, performance, DV and testing teams.
• Model and own uses-cases and workloads for custom silicon working closely with the CPU architecture, Performance  and IP teams to determine the overall power requirements.
• Analyze and deploy trade offs between CPU power and performance and drive detailed cost/benefit analysis and making recommendations for power reduction.
• Create test vectors with the performance, design verification and RTL teams to model the appropriate work loads, and the correct functionality scenarios for simulation
• Own power simulations, analysis, tuning, correlation, and rollup to the architecture, logic design, and physical design teams.
• Collaborate with the CAD and Physical design implementation teams on power estimation, simulation flow, and regression analysis
• Interact with software and system level teams to influence SoC and product level power

• 8 to 15 years experience in CPU power design including design analysis, benchmarking, modeling and simulation..
• Experience and working knowledge of CPU architectures and workload modeling for power.  RISC-V architecture familiarity and experience is a plus.
• Familiarity with Verilog and SystemVerilog RTL coding
• Experience in silicon design flow and evaluating PPA tradeoffs at architecture, logic and circuit design levels
• Knowledge of device physics, advanced process technology and circuit design fundamentals is a plus
• Experience in state-of-the art EDA tools for gate and transistor level power modeling and simulations.
• Python, TCL and other scripting languages
• Aptitude to problem-solve on the fly, innovate, drive decisions and bring the team along to deliver under aggressive schedules

• EE/ EECS degree with 8-15 years of industry experience